1. Field of the Invention
The present invention relates to delineation of wafers and in particular to delineation of junctions within wafers.
2. Description of the Prior Art
Silicon wafer fabrication techniques are used in the fabrication of integrated circuits. Integrated circuits form the basis of microelectromechanical devices (MEMS), computer processors, computer memory and many other devices. After the integrated circuits are formed they are tested to ensure that the fabrication process has produced operative devices.
Fault testing of integrated circuits involves probing the fabricated devices at different points and applying an electrical current between the probe points. Electrical characteristics between the probe points are then measured and provide an indication of whether or not the device is operating correctly.
There may be many causes of why a device does not operate correctly when probed. These could be a failure in the probing equipment or a failure in the device itself. If the failure is in the device and recurs frequently in devices made by the same process this could indicate that the manufacturing process needs to be adjusted to correct or prevent the failure.
One cause of failure in device can occur in the doping profile of a silicon wafer where one type of doping extends further through the wafer than required. This can lead to current leakage which can cause failures in devices. For example current leakage can occur in a p-n-p junction of a transistor where the two p layers are not sufficiently separated by the n layer. When a current is applied to the transistor it may leak through the n layer causing the transistor to malfunction.
If a fault in a device occurs in the doping profile of a silicon wafer this cannot be easily detected using microscopy as the different doping profiles of the silicon cannot be visually distinguished.
One current method used to view silicon implantation defects is to cut a sample from the device. The sample is then mounted and polished. The cross-sectional surface must have low roughness, no surface damage and high cleanliness. The sample receives a final polish using colloidal silica solution to provide the required sample quality. To improve the reproducibility of the results the surface can be coated with native oxide to eliminate any non-uniform charge distribution that remains after the polishing stages. The samples are then scanned with a SCM (scanning capacitance microscope). This system requires a skilled operator to operate the SCM to detect junction faults.